library verilog;
use verilog.vl_types.all;
entity cnt100_vlg_check_tst is
    port(
        ge_021          : in     vl_logic_vector(3 downto 0);
        shi_021         : in     vl_logic_vector(3 downto 0);
        sampler_rx      : in     vl_logic
    );
end cnt100_vlg_check_tst;
